1. Field of the Invention
The present invention generally relates to a thin film electronic component, and more particularly to a very thin film capacitor for a dynamic random access memory (DRAM) and a method of forming the same.
2. Description of the Related Art
DRAM capacitors are required to store approximately 10.sup.5 electrons, but simultaneously to fit into the limited area per bit specified in the memory design. Moore's Law, whereby the density of circuits on a chip increases exponentially with time (e.g., doubling every x years) equivalently stipulates that the area per bit decreases exponentially with time (e.g., halving every x years). Hence, there is an increasing problem in fitting the specified capacitance into the ever-decreasing specified area.
Current DRAM capacitors are fabricated in silicon technology, and use deep trenches or exfoliated structures to get the specified capacitance into the area per bit. However, as memory densities approach 10.sup.9 bits per chip, the requirement is becoming increasingly difficult to fulfil in silicon technology, and there is a wide interest in a group of alternative materials. By using high dielectric constant perovskite materials such as strontium titanate (STO) (bulk dielectric constant .epsilon..sub.bulk =300), or barium strontium titanate (BST) (.epsilon..sub.bulk exceeding 500 depending on composition), adequate capacitors could theoretically fit into the bit area up to and beyond 1 Gbit, provided the capacitors contain the dielectric in the form of a very thin film.
However, it has been found experimentally that the very high dielectric constants characteristic of the bulk, which constitute the advantage of the perovskite materials, are found in films having a thickness of about 400 nm. and thicker. However, in thinner films (e.g., less than 400 nm. thick), the effective dielectric constant drops with decreasing thickness. The film dielectric constant .epsilon..sub.film of a film of thickness d is approximately represented by the formula EQU .epsilon..sub.film =.epsilon..sub.bulk /(1+d.sub.0 /d),
where d.sub.0 is an empirical parameter, for example found to be 30 nm. in one instance of a series of STO films.
This is a fundamental problem, since the reduction in dielectric constant in thin films of high dielectric constant material is widely prevalent.
The above formula implies that the capacitance C relates to film thickness as: EQU C.varies..epsilon..sub.bulk /(d+d.sub.0),
showing that as film thickness d goes to zero, the right hand side of this expression saturates at .epsilon..sub.bulk /d.sub.0, and cannot increase further.
Hence, as films of high dielectric constant material such as STO (strontium titanate) and BST (barium strontium titanate) are made progressively thinner with the objective of approaching realistic capacitances per unit area, a film thickness is reached where no significant further increase in capacitance results from a further decrease in film thickness, and it becomes questionable as to whether they can reach the required specification for DRAM applications.
In C. Zhou and D. M. Newns, J. Appl. Phys. 82, 3081(1997), the present inventor, with C. Zhou, developed a theory of this effect which is able to explain both the characteristic dependence of the film dielectric constant .epsilon..sub.bulk on film thickness d (the dependence shown in the above equations), but also the dependence of .epsilon..sub.film on temperature T, which gives the theory some degree of credibility. The explanation of the phenomenon given by the theory of C. Zhou and D. M. Newns, J. Appl. Phys. 82, 3081 (1997) is as follows.
There is found theoretically to be a region at the surface of the dielectric film of high dielectric constant material where the dielectric constant is significantly depleted below that in the interior of the film, which for moderately thin films is the same as the bulk dielectric constant .epsilon..sub.bulk. This surface region, sometimes referred to as the "dead layer", of depleted dielectric constant is responsible for the reduced film dielectric constant .epsilon..sub.film.
The basic origin of the high dielectric constants in this class of materials is an interaction between the dipoles in each unit cell of the material which is favorable to a self-alignment of all the dipoles in a parallel direction so as to form a large dielectric polarization. However, at the interface between the dielectric film and one of the electrodes, dipoles do not see (e.g., are not near) any neighboring dipoles outside the interface, as there would be if the dipoles in question lay within the interior of a bulk crystal. Hence, the average number of neighboring dipoles is less for dipoles located near the interface. Thus, these dipoles have a reduced self-alignment tendency, due to the reduced number of neighbors, relative to dipoles located in bulk.
Hence, as a result of this reduced self-alignment tendency, surface dipoles are more weakly polarized than bulk ones, leading to a region of reduced dielectric constant near the interface with the electrodes, and hence to a reduced dielectric constant in the interface region of the film.
Another problem occurring with some perovskite dielectrics is that leakage current may be excessive, leading to an inconveniently short refresh time for the DRAM fabricated from such a material. A desirable limit on leakage resistance would be 10.sup.8 Ohm cm.sup.-2 per unit area of capacitance.